1. Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming metal-to-silicon contacts.
2. Description of Prior Art
Very large scale integrated circuit technology(VLSI) comprises the formation of isolated semiconductor devices within the surface of silicon wafers and interconnecting these devices with metallic wiring layers above the surface. This interconnection system usually consists of two or more levels of interconnection metallurgy, separated by insulation layers. The first layer of metallization(sometimes called the "book metal") is used to define small fundamental circuits, for example, a simple TTL gate comprised of two bi-polar transistors and two resistors. This metallization level provides the connections to the silicon devices themselves. In CMOS technology the polysilicon used for the gate electrode also provides local wiring such as connecting the gates of the n-channel and p-channel devices to each other. The first aluminum metallurgy level then provides connections to the source/drain areas and to the polysilicon gates. A second level of metal lines is then provided to interconnect these primary circuits into larger units and so on. A final layer of metallization is applied to connect the highest level of circuitry to pads which form the chip's external connections.
Connections between metal levels are made using metal filled via holes in an ILD (InterLevel-Dielectric) layer, which usually consists of silicon oxide, phosphosilicate glass(PSG), or borophosphosilicate glass(BPSG). Each level of metallurgy has a unique set of requirements which define it's composition and processing.
The first level must provide a low resistance(ohmic) contact to the silicon. Unlike metal-to-metal contacts, the metal-to-semiconductor contact is highly dependent on both the doping level and the doping type of the silicon. Current technology requires that the doping level of the silicon be of the order of 10.sup.20 atoms/cm.sup.3. This level of doping provides a sufficiently narrow depletion region and sufficient electron concentration to achieve adequate electron penetration of the interfacial energy barrier.
The metal chosen for this contact must have a low electron work function as well as a low resistivity. Earlier technology used aluminum because of it's low resistivity, good adhesion, and ease of processing. However, as the technology advanced, many modifications were necessary to cope with problems that arose with decreasing device size and increasing current requirements. Aluminum still remains the basic metal of choice for integrated circuit wiring although it's properties have been improved by the addition of small quantities of silicon(Si), tungsten(W), titanium(Ti) and copper(Cu).
Device miniaturization has brought on a number of obstacles which particularly affect the silicon-to-metal contacts. The sizes of the contacts have been reduced to the sub-micron range. Attempts to adapt the deposition of aluminum, either pure or alloyed with silicon, or other refractory metals, by evaporation or rf sputtering have required the use of tapered contact openings in order to achieve good step coverage. The contact openings can be tapered by a variety of etching techniques. Earlier methods used flowed photoresist to provide a taper which was replicated in the oxide contact opening by reactive-ion-etching(RIE). Other techniques used BPSG as the insulator which was flowed prior to metal deposition to give a large angle taper along the entire opening. Thalapaneni U.S. Pat. No. 5,238,872 describes a technique wherein a Ti-TiW-AL contact is formed into a BPSG layer. The upper part of the contact opening is widened by an initial isotropic chemical etching. Then RIE is used to provide a vertical wall to the base of the contact opening.
Recent advances in contact and via technology have lead to the use of tungsten for filling contact and via openings. Tungsten has a sufficiently low resistivity and it can be deposited at temperatures below 500.degree. C. by chemical vapor deposition(CVD) using the hydrogen or silane reduction of tungsten hexafluoride(WF.sub.6). The deposition is very conformal and results in remarkably good filling of vertical walled contact hole openings. Thus the need for space-wasting tapered contact openings is eliminated. A thin layer of Ti/TiW deposited into the contact hole opening prior to tungsten deposition, provides not only a better contact and diffusion barrier to the silicon, but also greatly improves the adhesion of the tungsten to the BPSG sidewall. Although the tungsten layer can be patterned to provide lateral wiring lines, the preferred method is to pattern the layer to expose only the studs and wire these with traditional aluminum interconnection metallurgy. The studs are referred to as W-plugs.
A prior art process for forming W-plug contacts on a silicon wafer 10 substrate is shown in FIG. 1(A-F). Referring first to FIG. 1A, there is shown a cross section of a portion of a self-aligned polysilicon gate MOSFET. Shown is implant 14 representing a source or drain and the polysilicon gate 16. The silicon oxide field isolation(FOX) 12 is also shown.
A layer of dielectric material is first deposited onto the silicon surface using low-pressure-chemical-vapor-deposition(LPCVD) or plasma-enhanced-chemical-vapor-deposition(PECVD). The layer is formed by the thermal decomposition of tetraethyl orthosilicate(TEOS) at temperatures below 650.degree. C. Doping of the layers with boron and phosphorous allows them to flow at low temperatures. In a typical application, a layer of undoped TEOS 18 is first deposited, forming silicon oxide. This is followed by a thicker layer of doped TEOS 20 which has the lower flowing temperature properties of BPSG. The initial undoped layer precludes any unwanted doping of the silicon by the BPSG.
As deposited, the surface of the BPSG layer replicates the non-planar surface of the silicon substrate. The wafer is annealed at 800.degree. C. to 900.degree. C. causing the BPSG to flow, thereby planarizing its upper surface(FIG. 1B). The BPSG is then etched back by reactive-ion-etching to reduce its thickness but maintaining the surface planarity as shown in FIG. 1C. Photoresist 22 is applied and the contact openings are patterned using standard photolithographic techniques. RIE is then used to form the vertical contact openings in the BPSG exposing the silicon active devices (FIG. 1D).
Although the flowing of the BPSG provides a smooth upper surface, its thickness is not necessarily exactly the same over all the contact areas of the chip. The thickness depends upon the topology of the surrounding area. Thus when the contact holes are subsequently opened by RIE, some over-etching will occur at contacts where the BPSG is thinner. Since the substrate diffusions are very shallow to begin with, any over-etching could jeopardize them. Additionally, because of device miniaturization, the area of the contact approaches that of the silicon active area. A slight misalignment of the contact mask could easily cause the contact opening to fall off the device implant area resulting in shorted junctions.
For these reasons an implant is made through the contact openings to re-enforce the active regions of the devices(represented by the arrows in FIG. 1D). The silicon in the exposed contact areas is implanted with the appropriate dopant to provide a concentration of 2.times.10.sup.14 to 2.times.10.sup.15 dopant atoms/cm.sup.2. Some products may require only one type of contact. For example, in NMOS technology the diffused contacts can be entirely of n-type. Here, the appropriate implant may be performed without masking. For complimentary MOS(CMOS) technology, where both n- and p-type contacts are required, a first implant of p-type dopant is directed at all the contacts. Then the p-type contacts are covered with a photoresist block-out mask and the n-contacts are implanted with a higher dose of n-type dopant to over-compensate the previous p-type implant. Using this procedure eliminates the need for an additional photolithographic step to shield the n-contacts.
Under the conventional procedure, these contact implants are next activated by rapid-thermal-annealing(RTA). This causes the BPSG to flow at the upper edge 24 (FIG. 1E) and severely encroach into the contact opening if the anneal temperature is above 950.degree. C. A Ti/TiN barrier metallization 26 (FIG. 1F) is then deposited and a barrier annealing is performed between 550.degree. and 700.degree. C. to secure a bond of the Ti to the silicon and to the BPSG. Finally a layer of CVD tungsten 30 is deposited to fill the contact opening. The encroachment of the BPSG into the contact opening causes a restriction to the filling of the contact hole by the tungsten 30 leaving a void 32 in the center. Depending upon the degree of the overhang and the size of the contact opening, the thin tungsten walls surrounding the void have the potential for subsequent electrical failure.